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| Page 1 of 10 IA16450 Preliminary Data Sheet Universal Asynchronous Receiver/Transmitter FEATURES * * * * * * Form, Fit, and Function Compatible with the National(c) NS16450 Packaging options available: 40 Pin Plastic or 44 Pin Plastic Leaded Chip Carrier Programmable Word Length, Stop Bits, and Parity Full Duplex Operation Programmable Baud Rate Generator - Division of any input clock by 1 to (216 -1) - Generates Internal 16 x clock Programmable Serial-Interface - 5-, 6-, 7- or 8-bit characters - Even, Odd, or No-Parity Bit Generation and Detection - 1-, 1 1/2-, or 2-Stop Bit Generation - Baud Generation of DC to 56k Prioritized Interrupt Control Internal Diagnostic/Loopback Capabilities * * The IA16450 uses innovASIC' innovative new f 3 Program to provide industry with parts that s other vendors have declared obsolete. By specifying parts through this program a customer is assured of never having a component become obsolete again. This advanced information sheet assumes the original part has been designed in, and so provides a summary of capabilities only. For new designs contact innovASIC for more detailed information. National is a copyright trademark of National Semiconductor Corporation Package Pinout DCD_n DSR_n (41) VCC (40) (39) (38) (37) (36) (35) (34) (33) (32) (31) (30) (29) (28) (27) (26) (25) (24) (23) (22) (21) VCC RI_n DCD_n (44) (43) (42) DSR_n CTS_n MR OUT1_n DTR_n RTS_n OUT2_n INTR N. C. A0 A1 A2 ADS_n CSOUT DDIS RD RD_n CSOUT ADS_n WR_n RD_n WR VSS XOUT N. C. RD DDIS XIN D5 D6 D7 RCLK SIN N. C. SOUT CS0 CS1 CS2_n BAUDOUT_n (40) (6) (5) (4) (3) (2) (1) RI_n D0 D1 D2 D3 D4 D5 D6 D7 RCLK SIN SOUT CS0 CS1 CS2_n BAUDOUT_n XIN XOUT WR_n WR VSS (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) (16) (17) (18) (19) (20) CTS_n N. C. D4 D3 D2 D1 40 Pin DIP D0 IA16450 (7) (8) (9) (10) (11) (12) (13) (14) (15) (16) (17) (18) (19) (20) (21) (22) (23) (24) (25) (26) (27) (28) (39) (38) MR OUT1_n DTR_n RTS_n OUT2_n N. C. INTR N. C. A0 A1 A2 IA16450 44 Pin LCC (37) (36) (35) (34) (33) (32) (31) (30) (29) Copyright (c) 1999, InnovASIC Inc. Customer Specific IC Solutions Page 2 of 10 IA16450 Preliminary Data Sheet Universal Asynchronous Receiver/Transmitter The IA16450 is a form, fit and function compatible part to the National NS16450 Univeral Asynchronous Receiver/Transmitter. The IA16450 function receives and transmits data in a variety of configurations including 5, 6, 7 or 8 bit data words, odd, even or no parity, and 1, 1.5, and 2 stop bits. This megafunction includes an internal Baud Rate Generator and Interrupt Control. A block diagram is shown in Figure 1. Functional Block Diagram Figure 1 INTERNAL DATA BUS D7:D0 DATA BUS BUFFER RECEIVER BUFFER REGISTER RECEIVER SHIFT REGISTER SIN LINE CONTROL REGISTER RECEIVER TIMING & CONTROL RCLK A0 A1 A2 DIVISOR LATCH (LSB) BAUDOUT_n BAUD GENERATOR DIVISOR LATCH (MSB) CS0 CS1 CS2_n ADS_n MR RD RD_n WR WR_n DDIS CSOUT RTS_n XIN XOUT MODEM CONTROL REGISTER MODEM CONTROL LOGIC MODEM STATUS REGISTER CTS_n DTR_n DSR_n DCD_n RI OUT1_n OUT2_n TRANSMITTER HOLDING REGISTER TRANSMITTER SHIFT REGISTER SOUT DECODE AND CONTROL LOGIC LINE STATUS REGISTER TRANSMITTER TIMING & CONTROL INTERRUPT ENABLE REGISTER INTERRUPT CONTROL LOGIC INTR INTERRUPT ID REGISTER Copyright (c) 1999, InnovASIC Inc. Customer Specific IC Solutions Page 3 of 10 IA16450 Preliminary Data Sheet Universal Asynchronous Receiver/Transmitter I/O Signal Description Table 1 below describes the I/O characteristics for each signal on the IC. The signal names correspond to the signal names on the pinout diagrams provided. Table 2 refers to the address register map. Table 3 refers to the Preliminary A. C. Characteristics. Figure 2 illustrates the Preliminary Timing Waveforms for this device. Environmental/Qualification Levels are listed in Table 4. Table 1 Name MR Type I Description Master Reset - Active high - Clears all registers (except the receiver buffer, transmitter holding and divisor latches) to their initial state. Resets internal control logic to its initial state Register Address - Active high - This bus selects one of the internal UART registers (refer to table 1). Note the state of the divisor latch access bit (DLAB - the msb of the line control register) must be set high to access the divisor latches and low to access the receiver buffer or the interrupt enable register. Data Input Bus - Active high - Serves as input data when writing to internal UART registers. Chip Select 0 - Active high - When CS0, CS1 and CS2 are active the megafunction is selected. Read and write transactions to internal UART registers are then possible. Chip Select 1 - Active high - When CS0, CS1 and CS2 are active the megafunction is selected. Read and write transactions to internal UART registers are then possible. Chip Select 2 - Active low - When CS0, CS1 and CS2 are active the megafunction is selected. Read and write transactions to internal UART registers are then possible. Address Strobe - Active low - Gating signal to the Address input latch. The positive edge of ADS_n latches the state of the register address bus into the Address input latch. If address signals are guaranteed to be stable for the duration of a read or write cycle, ADS_n may be tied low thus forcing the Address input latch to be transparent. Read Control - Active High - when RD is high or RD_n is low and the UART is selected, read transactions from internal UART registers are possible. A(2:0) I DIN(7:0) CS0 I I CS1 I CS2_n I ADS_n I RD I Copyright (c) 1999, InnovASIC Inc. Customer Specific IC Solutions Page 4 of 10 IA16450 Preliminary Data Sheet Universal Asynchronous Receiver/Transmitter Name RD_n Type I Description Read Control - Active low - when RD is high or RD_n is low and the UART is selected, read transactions from internal UART registers are possible. Write Control - Active High - when WR is high or WR_n is low and the UART is selected, write transactions to internal UART registers are possible. Write Control - Active low - when WR is high or WR_n is low and the UART is selected, write transactions to internal UART registers are possible. Serial Data Input - Active High - Receive data to the UART Receive Clock - The 16x baud rate clock used by the receiver section of the UART. Clear To Send - Active Low - Active state indicates that the MODEM or data set is ready to exchange data. A change in state of this input is recorded in the DCTS bit (bit 0) of the MODEM Status register. Whenever CTS_n changes state, an interrupt is generated if the MODEM Status interrupt is enabled. The complement of this input is recorded in the CTS (bit 4) bit of the MODEM Status register Data Set Ready - Active Low - Active state indicates that the MODEM or data set is ready to establish the communications link with the UART. A change in state of this input is recorded in the DDSR bit (bit 1) of the MODEM Status register. Whenever DSR_n changes state, an interrupt is generated if the MODEM Status interrupt is enabled. The complement of this input is recorded in the DSR (bit 5) bit of the MODEM Status register Data Carrier Detect - Active Low - Active state indicates that the data carrier has been detected by the MODEM or data set. A change in state of this input is recorded in the DDCD bit (bit 3) of the MODEM Status register. Whenever DCD_n changes state, an interrupt is generated if the MODEM Status interrupt is enabled. The complement of this input is recorded in the DCD (bit 7) bit of the MODEM Status register WR I WR_n I SIN RCLK CTS_n I I I DSR_n I DCD_n I Copyright (c) 1999, InnovASIC Inc. Customer Specific IC Solutions Page 5 of 10 IA16450 Preliminary Data Sheet Universal Asynchronous Receiver/Transmitter Name RI_n Type I Description Ring Indicator - Active Low - Active state indicates that the ring signal has been detected by the MODEM or data set. A change in state of this input is recorded in the TERI bit (bit 2) of the MODEM Status register. Whenever DSR_n changes state, an interrupt is generated if the MODEM Status interrupt is enabled. The complement of this input is recorded in the RI (bit 6) bit of the MODEM Status register Data Output Bus - Active high - Serves as output data when reading from internal UART registers. Driver Disable - Active High - Active State indicates that the CPU is reading data from the UART. This output is intended as a disable or direction control between the UART and CPU. Chip Select Output - Active High - Active State indicates that the megafunction has been selected by use of the CS0, CS1 and CS2_n inputs. Serial Data Out - Active High - Serial (transmit) data out. This signal is set to the marking (logic 1) state upon master reset. Baud Out - Active Low - The 16x baud rate clock used by the transmitter section of the UART. This output is controlled by the programmable baud rate generator. Request to Send - Active Low - This output indicates that the UART is ready to exchange data. This output is controlled by writing to the RTS (bit 1) bit of the control register. Data Terminal Ready - Active Low - This output indicates that the UART is ready to establish a communications link. This output is controlled by writing to the DTR (bit 0) bit of the control register. Discrete Output - Active Low - One of two user-programmable discrete outputs. This output is controlled by writing to the OUT1 (bit 2) bit of the control register. Discrete Output - Active Low - One of two user-programmable discrete outputs. This output is controlled by writing to the OUT2 (bit 3) bit of the control register. Interrupt - Active High - Indicates that an enabled interrupt has had its interrupt condition met. DOUT(7:0) DDIS O O CSOUT O SOUT BAUDOUT_n O O RTS_n O DTR_n O OUT1_n O OUT2_n O INTR O Copyright (c) 1999, InnovASIC Inc. Customer Specific IC Solutions Page 6 of 10 IA16450 Preliminary Data Sheet Universal Asynchronous Receiver/Transmitter Name XIN Type I Description External Crystal Input. This signal iniput is used in conjuction with XOUT to form a feedback circuit for the baud rate generator' oscillator. If a clock signal will be generated offs chip, then it should drive the baud rate generator through this pin External Crystal Output. This signal output is used in conjuction with XIN to form a feedback circuit for the baud rate generator' oscillator. If the clock signal will be generated s off-chip, then this pin is unused. Ground. +5V power. XOUT O VSS VCC P P IA16450 Register Address Map Table 2 DLAB 0 1 0 1 X X X X X X A2 0 0 0 0 0 0 DATA A1 0 0 0 0 1 1 0 0 1 1 A0 0 0 1 1 0 1 0 1 0 1 REGISTER DESCRIPTION Receiver Buffer - Read Only Transmitter Holding Register - Write Only Divisor Latch (LSB) Interrupt Enable Register Divisor Latch (MSB) Interrupt ID Register Line Control Register MODEM Control Register Line Status Register MODEM Status Register Scratch 1 1 1 1 Copyright (c) 1999, InnovASIC Inc. Customer Specific IC Solutions Page 7 of 10 IA16450 Preliminary Data Sheet Universal Asynchronous Receiver/Transmitter AC Electrical Characteristics Table 3 tADS tAH tAR tAS tAW tCH tCS tCSC tCSR tCSW tDH tDS tHZ tRA tRC tRCS tRD tRDD tRVD tWA tWC tWCS tWR RC WC Symbol Parameter Address Strobe Width Address Hold Time RD, RD_n Delay from Address Address Setup Time WR, WR_n Delay from Address Chip Select Hold Time Chip Select Setup Time Chip Select Output Delay from Select RD, RD_n Delay fron Select WR, WR_n Delay fron Select Data Hold Time Data Setup Time RD, RD_n to Floating Data Delay Address Hold Time from RD, RD_n Read Cycle Delay Chip Select Hold Time from RD, RD_n RD, RD_n Strobe Width RD, RD_n to Driver Disable Delay Delay from RD, RD_n to Data Address Hold Time from WR, WR_n Write Cycle Delay Chip Select Hold Time from WR, WR_n WR, WR_n Strobe Width Read Cycle = tAR + t RD + t RC Write Cycle = t AW + t WR +tWC (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) Min 25 0 20 25 20 0 25 Max 33 20 20 10 20 0 0 36 0 60 20 31 0 36 0 60 115 115 25 Note 1: Applicable only when ADS_n is tied low. Copyright (c) 1999, InnovASIC Inc. Customer Specific IC Solutions Page 8 of 10 IA16450 Preliminary Data Sheet Universal Asynchronous Receiver/Transmitter Timing Waveforms Figure 2 tADS ADS_n tAS A2,A1,A0 VALID tCS CS2_n,CS1,CS0 VALID tCSC CSOUT tCSW tAW WR_n,WR RD_n,RD tDS DATA,D0:D7 t DH ACTIVE t WR tWC WC ACTIVE ACTIVE Write Cycle tAH t CH tWA tWCS VALID DATA Read Cycle t ADS ADS_N tAS A2,A1,A0 VALID tCS CS2_n,CS1,CS0 VALID tCSC CSOUT t CSR tAR RD_n,RD WR_n,WR t RDD DDIS t RVD DATA,D0:D7 VALID DATA tHZ tRDD tRD ACTIVE tRC ACTIVE ACTIVE tAH tRA tCH tRCS RC Copyright (c) 1999, InnovASIC Inc. Customer Specific IC Solutions Page 9 of 10 IA16450 Preliminary Data Sheet Universal Asynchronous Receiver/Transmitter Qualification Levels Table 4 Part Number IA16450-PDW40C IA16450-PLC44C IA16450-PDW40I IA16450-PLC44I Environmental/ Qual Level Commercial Commercial Industrial Industrial The following diagram depicts the innovASIC Product Identification Number. IAXXXXX-PPPPNNNT/SP Special Processing: S = Space Q = MIL-STD-883 Temperature: C = Commercial I = Industrial M = Military Number of Leads Package Type: Per Package Designator Table IC Base Number innovASIC Designator Copyright (c) 1999, InnovASIC Inc. Customer Specific IC Solutions Page 10 of 10 IA16450 Preliminary Data Sheet Universal Asynchronous Receiver/Transmitter Package Designator Table Package Type Ceramic side brazed Dual In-line Cerdip with window Ceramic leaded chip carrier Cerdip without window Ceramic leadless chip carrier PLCC Plastic DIP standard (300 mil) Plastic DIP standard (600 mil) Plastic metric quad flat pack Plastic thin quad flat pack Skinny Cerdip Small outline plastic gull-wing(150 mil body) Small outline medium plastic gull-wing (207 mil body) Small outline narrow plastic gull wing (150 mil body) Small outline wide plastic gull wing (300 mil body) Skinny Plastic Dip Shrink small outline plastic (5.3mm .208 body) Thin shrink small outline plastic Small outline large plastic gull wing (330 mil body) Thin small outline plastic gull-wing (8 x 20mm) [TSOP] PGA BGA innovASIC Designator CDB CDW CLC CD CLL PLC PD PDW PQF PTQ CDS PSO PSM PSN PSW PDS PS PTS PSL PST CPGA CBGA Contact innovASIC for other package and processing options. Copyright (c) 1999, InnovASIC Inc. Customer Specific IC Solutions |
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